1. Field of the Disclosure
Generally, the present disclosure relates to the fabrication of integrated circuits and semiconductor devices, and, more particularly, to forming silicon-on-insulator (SOI) semiconductor devices.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, application specific integrated circuits (ASICs) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. In a wide variety of electronic circuits, field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced for forming field effect transistors (FETs), wherein, for many types of complex circuitry, metal-oxide-semiconductor (MOS) technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. Miniaturization and increase of circuit densities represent ongoing demands.
A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed between the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially affects the performance of MOS transistors. Thus, as the speed of creating the channel, which depends on the conductivity of the gate electrode, and the channel resistivity substantially determine the transistor characteristics, the scaling of the channel length is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits. As the channel length is reduced, the thickness of the gate dielectric is also reduced. The scaling of the gate dielectric is limited by several factors, such as defects, power supply voltage, time-dependent dielectric breakdown and leakage currents.
When forming source/drain regions of semiconductor devices, in particular for silicon-on-insulator (SOI) substrates, control of various capacitances is very important. For instance, with regard to applications to ring oscillators, ring oscillator speed degrades with increasing gate/drain capacitance. This also includes contributing capacitances between the gate and the semiconductor material extending along the sidewalls of the gate structure. In order to minimize this capacitance, the distance from the semiconductor material extending along the sidewalls of a gate structure may be chosen to be large. This may be achieved by forming thicker spacers. However, while a large thickness of spacers would suppress the above-mentioned parasitic capacitance, it would contrast another requirement, said other requirement would be to have a close proximity of the raised source/drain region to a channel region so as to have a sufficient overlap capacitance between these two regions.
In view of the above, the present disclosure relates to semiconductor devices, in particular, transistor devices and techniques for forming transistor devices, allowing for fast ring oscillator speed high-frequency, while having sufficient overlap capacitance, which may be integrated in the process flow of fully depleted silicon-on-insulator (FDSOI) manufacturing.